Application specific integrated circuits (ASICs) are used in a wide range of electronic devices. ASICs incorporate designs specifically matched to the electronic device, often reflecting circuit designs of the device manufacturer. In such cases, the ASIC is designed by an IC designer or user employed by or associated with the device manufacturer. Ordinarily, the device manufacturer does not have the capability of actually manufacturing the ASIC, so it is common for such device manufacturers to select an IC foundry to perform actual manufacture of the ASIC. In the design process, the designer uses tools supplied by the IC manufacturer so that the resulting chip will be compatible to the IC manufacturer's fabrication requirements.
LSI Logic Corporation of Milpitas, Calif., supplies tools and a design methodology based on RapidChip® platform ASICs. The RapidChip platforms are chips containing all silicon-based layers of an IC, but without metal interconnection layers. The silicon layers are configured into gates that can be configured into cells using LSI Logic Corporation's CoreWare® logic and design concepts. The chip designer designs the additional metal layers for the base platform to thereby configure the chip into a custom ASIC employing the customer's intellectual property. More particularly, the chip designer might use LSI Logic Corporation's RapidWorx® design system with included FlexStream® processes to design and test an ASIC based on the RapidChip platform configured to the customer's custom application. The RapidChip platform permits the development of complex, high-density ASICs in minimal time with significantly reduced design and manufacturing risks and costs.
During the design process, it is common to define the ASIC in a hardware description language (HDL) such as Verilog, representing the circuit in text, rather than graphically. The HDL description defines the functions performed by the cells and the relationship to input and output pins (targets) of the cells. The HDL description of an integrated circuit can be written at an intermediate level known as a register transfer language (RTL). The RTL description is transportable to other environments through the use of tools. For example, a logic synthesis tool can convert a RTL description of an integrated circuit into a gate-level netlist for a given technology library. The netlist can then be applied to a simulator, such as a Synopsys VCS simulator, for test purposes.
Integrated circuits are often described in multiple files. Some files may define circuit portions configured to an IC manufacturer's standard logic circuits, and other files may define portions configured to the user's intellectual property. A problem arises, however, when applying a multi-file circuit description to another environment.
A list file is a directory that identifies RTL files and their paths. For example, a call to a Synopsys VCS simulator might list RTL files and their full paths as:
vcs\<various options>\/full/path/to/file1.v\/full/path/to/file2.v\. . ./full/path/to/filen.vwhere <various options> identifies VCS simulator options. The code might be simplified using a list file that identifies, as a design list, the paths to the files:
vcs\<various options>\-f design.1stwhere design.lst identifies the files and their respective paths:
/full/path/to/file1.v/full/path/to/file2.v. . ./full/path/to/filen.v
A problem arises that the file paths may change when files are moved in the directory structure. Typically, the list file is created containing hard-coded paths or relative path types to locate objects. The list file correlates paths in the receiving environment to paths in the sending environment. However, the list file must be updated upon movement of the design file to a different environment. As an alternative to updating, the list file may contain references to multiple links that correlate a current location to locations in each of a plurality of environments. However, both of these solutions are time consuming, and adversely affects the time required for the design phase.
The present invention is directed to an automated technique to manage IC design file paths as the design files are applied to different environments.